1. Field of the Invention
The present invention generally relates to a manufacturing method for a semiconductor device. More particularly, the present invention relates to a manufacturing method for a semiconductor device used as a power semiconductor device and can suitably be employed for, for example, a vertical type MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor) or a MOSIC as a single unit or with the incorporation of a power semiconductor device.
2. Related Arts
Recently, a vertical type power MOSFET has been used in many industrial fields for various features thereof such as high frequency characteristics, fast switching speed and low power driving. The Nikkei Electronics (Nikkei-McGraw-Hills, Inc., May 19, 1986, pp. 165-188) says that the focus of the development of the power MOSFET has shifted to the low withstand voltage type and the high withstand voltage type, and that the ON-resistance of the power MOSFET having a withstand voltage of 100 V or less has been lowered down to a level of 10 m.OMEGA. for the reason that channel width per unit area has been widened by using the microprocessing of LSI for the manufacture of the power MOSFET or by improving the shape of the power MOSFET. The description of this magazine centers around the prevailing vertical type power MOSFET using DMOS type (double diffusion type) cells, reasoning that the DMOS type has productional advantages of high yield and low cost owing to the use of the planar process featured by the use of a flat main surface of a silicon wafer for the channel part.
On the other hand, along with the spread of the vertical power MOSFET, there is an increasing demand for lower loss and lower cost, while the ON-resistance reduction by means of microprocessing and cell shape improvement has reached the limits. According to the Japanese Unexamined Patent Publication No. 63-266882, for example, the DMOS type has the minimal point from which the ON-resistance will not decrease however small the unit cell dimension is made by microprocessing, and it has been known that the major cause of the existence of the minimal point is an increase in the JFET (junction field effect transistor) resistance constituting a component of the ON-resistance. Furthermore, as disclosed in the Japanese Unexamined Patent Publication No. 2-86136, the unit cell dimension with which the ON-resistance takes the minimal point is approximately 15 .mu.m under the current microprocessing technology.
Various constructions have been proposed in an attempt to break through this limit. Common to these proposals is a construction in which a groove is formed on an element surface and a channel part is formed on a side surface of the groove, and this construction can substantially reduce the above JFET resistance. Furthermore, in a construction in which the channel part is formed on the groove side surface, even if the unit cell dimension is reduced, the consequent increase in the JFET resistance is negligible. Therefore, there is no limits that the ON-resistance takes the minimal point against the reduction in the unit cell dimension unlike the description in the Japanese Unexamined Patent Publication No. 63-266882, and the unit cell dimension can further be reduced to the limits of the microprocessing downwardly exceeding 15 .mu.m.
Examples of the conventional manufacturing method with the above construction with the channel part on the groove side surface have been disclosed in the International Publication No. PCT WO93/03502 and the Japanese Unexamined Patent Publication No. 62-12167, for example, and the results of investigation have been disclosed in the ISPSD '93 pp.135-140.
FIG. 25(a) and FIG. 25(b) are a plane view and a cross-sectional view of the MOSFET disclosed in the International Publication No. PCT WO93/03502, and FIGS. 26 though 37 are cross-sectional views of the MOSFET illustrating the manufacturing process thereof according to the same publication.
The above manufacturing process will now be described.
First of all, as illustrated in FIG. 26, a wafer 21 is prepared with an n.sup.- -type epitaxial layer 2 developed on the main surface of a semiconductor substrate 1 made of n.sup.+ -type silicon. This semiconductor substrate 1 has an impurity concentration of approximately 10.sup.20 cm.sup.-3, while the n.sup.- type epitaxial layer 2 is developed to a thickness of approximately 7 .mu.m and an impurity concentration of approximately 10.sup.16 cm.sup.-3. A field oxide film 60 is formed to a thickness of approximately 60 nm by thermally oxidizing the main surface of the wafer 21, and then a resist film 61 is deposited and patterned by the publicly known photolithographic technique with the central part thereof open, the location of which being coincided with a location of cell formation. Then, boron ions (B.sup.+) are implanted through the field oxide film 60 by using the resist film 61 as a mask.
After removing the resist film 61, as illustrated in FIG. 27, a p-type diffusion layer 62 is formed to a junction depth of approximately 3 .mu.m. The p-type diffusion layer 62 ultimately becomes a part of a p-type base layer 16 (described herein later), and plays a role of improving the surge resistance by stably causing breakdown to the bottom part of the p-type diffusion layer 62 when a high voltage is applied to between a drain electrode and a source electrode.
Next, as illustrated in FIG. 27, a silicon nitride film 63 is deposited to a thickness of approximately 200 nm on the main surface of the wafer 21. The silicon nitride film 63 is patterned into a lattice-like open pattern with openings with a pitch (dimension of a unit cell 15) a. Incidentally, mask alignment is applied to the open pattern so that the p-type diffusion layer 62 can be positioned in the central part of the pitch.
Following the above, as illustrated in FIG. 28, the field oxide film 60 is etched by using the silicon nitride film 63 as a mask, and then a groove 64 is formed by etching the n.sup.- -type epitaxial layer 2 to a depth of approximately 1.5 .mu.m.
As illustrated in FIG. 29, this time, the groove 64 is thermally oxidized by using the silicon nitride film 63 as a mask, which is a well known oxidizing technique as LOCOS (local oxidation of silicon). By this oxidation, a selective oxide film, i.e., a LOCOS oxide film 65 is formed, and concurrently a U-groove 50 is formed on the surface of the n.sup.- -type epitaxial layer 2 eroded by the LOCOS oxide film 65 and the shape of the groove 50 is fixed.
Then, as illustrated in FIG. 30, boron ions are implanted through a thin field oxide film 60 by using the LOCOS oxide film 65 as a mask to form the p-type base layer 16. In this process, the boundary surface between the LOCOS oxide film 65 and the field oxide film 60 is coincided with a self-alignment position, and accordingly a region into which boron ions are to be implanted can exactly be defined.
In the next process, as illustrated in FIG. 31, thermal diffusion is performed to obtain a junction depth of approximately 3 .mu.m. By this thermal diffusion, the p-type diffusion layer 62 previously formed in the process illustrated in FIG. 27 and the diffusion layer of the boron ions implanted in the process illustrated in FIG. 30 are integrated into the single p-type base layer 16, and both end surfaces of the p-type base layer 16 are self-alignedly defined in the position of the side walls of the U-groove 50.
Now, as illustrated in FIG. 32, phosphorous ions are implanted through the thin field oxide film 60 by using both a resist film 66 patterned by a pattern left on the central part of the surface of the p-type base layer 16 surrounded by the LOCOS oxide film 65 formed on the surface of the wafer 21 by a lattice-like pattern and the LOCOS oxide film 65 to form the n.sup.+ -type source layer 4. In this process as well, like the ion implantation performed with boron ions in the process illustrated in FIG. 30, the boundary part between the LOCOS oxide film 65 and the field oxide film 60 is coincided with a self-alignment position, and accordingly a region into which phosphorous ions are to be implanted can exactly be defined.
After the above, as illustrated in FIG. 33, the n.sup.+ -type source layer 4 is formed and concurrently the channel 5 is set up by thermal diffusion to a junction depth of 0.5 to 1 .mu.m. By this thermal diffusion, the end surface being in contact with the U-groove 50 in the region of the n.sup.+ -type source layer 4 is self-alignedly defined.
As a result of the processes illustrated in FIGS. 30 through 33, the junction depth and shape of the p-type base layer 16 can be fixed.
As illustrated in FIG. 34, now, the LOCOS oxide film 65 is removed by wet etching to expose an inside wall 51 of the U-groove 50, and then a gate oxide film 8 is formed to a thickness of approximately 60 nm by thermal oxidation.
Next, as illustrated in FIG. 35, a polysilicon film is deposited to a thickness of approximately 400 nm on the main surface of the water 21.
Following the above, as illustrated in FIG. 36, boron ions are implanted through the oxide film 67 by using the patterned resist film 68 as a mask in preparation for forming a p.sup.+ -type base contact layer 17.
Then, as illustrated in FIG. 37, the p.sup.+ -type base contact layer 17 is formed by the thermal diffusion to a junction depth of approximately 0.5 .mu.m.
Subsequently, as illustrated in FIG. 25(b), an interlayer insulating film 18 is formed with BPSG (boron phosphate silicate glass) on the main surface of the wafer 21, and contact holes are made in parts of the interlayer insulating film 18 to expose the p.sup.+ -type base contact layer 17 and the n.sup.+ -type source layer 4. Furthermore, a source electrode 19 is formed with an aluminum film to achieve an ohmic contact between the source electrode 19 and the p.sup.+ -type base contact layer 17 and n.sup.+ -type source layer 4 through the contact holes. In addition, a passivation film (not illustrated) for protecting the aluminum film is formed by the plasma CVD method or the like using silicon nitride. On the other hand, on the back surface of the wafer 21 is formed a drain electrode 20 with three layers of a Ti film, a Ni film and a Au film and ohmically contacted with the n.sup.+ -type semiconductor substrate 1.